Difference between revisions of "WDA 2008"
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New research frontiers are therefore open for exploration that will lead to the discovery and development of dependable architectures, this includes research at all design levels: circuit, architecture, compiler, OS and network. This workshop aims to become a forum for academia and industry to discuss and present ideas and recent developments in the design and evaluation of dependable architectures both software and hardware. | New research frontiers are therefore open for exploration that will lead to the discovery and development of dependable architectures, this includes research at all design levels: circuit, architecture, compiler, OS and network. This workshop aims to become a forum for academia and industry to discuss and present ideas and recent developments in the design and evaluation of dependable architectures both software and hardware. | ||
− | + | ==Call for papers== | |
+ | Two kinds of papers are invited: | ||
+ | 1. Technical papers (at least 6 pages) for relatively mature ideas. | ||
+ | 2. Position papers (3 pages maximum) on directions for research and development. | ||
+ | |||
+ | Please submit an electronic copy of your paper (in PDF) in two column format with at least 10pt font. Submission instructions and other workshop related information will appear here. | ||
+ | |||
+ | The selected papers will be made available online. However, publication in WDA does not preclude later publication at regular conferences or journals. | ||
+ | |||
+ | Topics of interest include but not limited: | ||
+ | |||
+ | * Multi-core Dependability Challenges and Opportunities | ||
+ | * Compiler and Operating System Aware Dependability | ||
+ | * Dependable On-chip Interconnect and Routing | ||
+ | * Soft-error measurement, modeling and mitigation techniques | ||
+ | * Lifetime reliability | ||
+ | * Better than worst case design | ||
+ | * Dynamic verification techniques | ||
+ | * Approximate processing and reliability | ||
+ | * Process Variation Aware Design | ||
+ | * Techniques for reducing impact of variability: | ||
+ | ** Temperature, Voltage droops, dI/dT, Crosstalk | ||
+ | * Fault-aware computing: | ||
+ | ** Fault injection, detection, Error modeling, Fail-safe and fail-stop systems, Time and space redundancy, dRedundancy/dEnergy (dR/dE) -efficient architectures | ||
+ | * Compiler/architecture/OS synergistic techniques and interaction for dependability | ||
==Important Dates== | ==Important Dates== |
Latest revision as of 00:12, 31 May 2012
WDA 2008 | |
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Workshop on Dependable Architectures
| |
Dates | Nov 9, 2008 (iCal) - Nov 9, 2008 |
Homepage: | www.cs.ucy.ac.cy/carch/wda08 |
Location | |
Location: | Lake Como, Italy |
Loading map... | |
Important dates | |
Submissions: | Sep 8, 2008 |
Notification: | Oct 6, 2008 |
Camera ready due: | Oct 13, 2008 |
Table of Contents | |
WDA-3 2008
3rd Workshop on Dependable Architectures (extends previously held Workshop on Architectural Reliability - WAR)
In conjunction with the
41st International Symposium on Microarchitecture (MICRO-41)
Sunday, November 9, 2008 Lake Como, Italy
Scope
Current computer technology trends present to the hardware and software designer novel opportunities to improve performance and at the same time many challenges to overcome. One of the formidable challenges is to provide dependable operation - in terms of reliability and availability - for a system made of unreliable components.
The combination of various developments brought dependability to prominence: soft-error rate is projected to increase with scaling; variability due to non-deterministic placement of dopant atoms and channel length is increasing design margins; better than worst-case design techniques for power/performance require error detection/correction; aggressive application of power-saving mechanisms such as clock- and Vdd-gating are increasing voltage droops; the verification manpower budget is becoming a significant part of the design effort; oxide breakdown and electromigration are decreasing processor lifetimes.
New research frontiers are therefore open for exploration that will lead to the discovery and development of dependable architectures, this includes research at all design levels: circuit, architecture, compiler, OS and network. This workshop aims to become a forum for academia and industry to discuss and present ideas and recent developments in the design and evaluation of dependable architectures both software and hardware.
Call for papers
Two kinds of papers are invited: 1. Technical papers (at least 6 pages) for relatively mature ideas. 2. Position papers (3 pages maximum) on directions for research and development.
Please submit an electronic copy of your paper (in PDF) in two column format with at least 10pt font. Submission instructions and other workshop related information will appear here.
The selected papers will be made available online. However, publication in WDA does not preclude later publication at regular conferences or journals.
Topics of interest include but not limited:
- Multi-core Dependability Challenges and Opportunities
- Compiler and Operating System Aware Dependability
- Dependable On-chip Interconnect and Routing
- Soft-error measurement, modeling and mitigation techniques
- Lifetime reliability
- Better than worst case design
- Dynamic verification techniques
- Approximate processing and reliability
- Process Variation Aware Design
- Techniques for reducing impact of variability:
- Temperature, Voltage droops, dI/dT, Crosstalk
- Fault-aware computing:
- Fault injection, detection, Error modeling, Fail-safe and fail-stop systems, Time and space redundancy, dRedundancy/dEnergy (dR/dE) -efficient architectures
- Compiler/architecture/OS synergistic techniques and interaction for dependability
Important Dates
Paper due: September 8, 2008 (11.59PM PDT) Notification: October 6, 2008 Final paper due: October 13, 2008
Co-Organizers
Yiannakis Sazeides, University of Cyprus Osman Unsal, Barcelona Supercomputing Center Oguz Ergin, TOBB University of Economic and Technology
Program Committee
- Todd Austin University of Michigan
- David Brooks Harvard University
- Veerle Desmet Ghent University
- Oguz Ergin TOBB University of Economic and Technology
- Babak Falsafi EPFL
- C. Mani Krishna UMass, Amherst
- Shubu Mukherjee Intel
- Onur Mutlu Microsoft
- Jude Rivers IBM
- Yiannakis Sazeides University of Cyprus
- Osman Unsal Barcelona Supercomputing Center
- Xavi Vera Intel
- David Kaeli Northeastern University
Previous Workshops
WAR-1 (2005) WAR-2 (2006)
Webmaster:
Constantinos Kourouyiannis, University of Cyprus
This CfP was obtained from WikiCFP
Acronym | WDA 2008 + |
Camera ready due | October 13, 2008 + |
End date | November 9, 2008 + |
Event type | Workshop + |
Has PC member | Todd Austin +, David Brooks +, Veerle Desmet +, Oguz Ergin +, Babak Falsafi +, C. Mani Krishna +, Shubu Mukherjee +, Onur Mutlu +, Jude Rivers +, Yiannakis Sazeides +, Osman Unsal +, Xavi Vera + and David Kaeli + |
Has coordinates | 45° 59' 30", 9° 15' 54"Latitude: 45.991758333333 Longitude: 9.2648805555556 + |
Has location city | Lake Como + |
Has location country | Category:Italy + |
Homepage | http://www.cs.ucy.ac.cy/carch/wda08 + |
IsA | Event + |
Notification | October 6, 2008 + |
Start date | November 9, 2008 + |
Submission deadline | September 8, 2008 + |
Title | Workshop on Dependable Architectures + |