Difference between revisions of "HEART 2012"

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(New page: {{Event |Acronym=HEART 2012 |Title=Highly Efficient Accelerators and Reconfigurable Technologies |Type=Workshop |Field=efficient computing |Start date=2012/05/31 |End date=2012/06/01 |Home...)
 
 
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* Architectures and systems:
 
* Architectures and systems:
−
- Novel systems/platforms for efficient acceleration based on FPGA,
+
** Novel systems/platforms for efficient acceleration based on FPGA, GPU, CELL/B.E and other devices
−
GPU, CELL/B.E and other devices
+
** Heterogeneous processors/systems for scalable, high-performance, high-reliability and/or low-power computation
−
- Heterogeneous processors/systems for scalable, high-performance,
+
** Reconfigurable/configurable hardware and systems including IP-cores, embedded systems, SoCs and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
−
high-reliability and/or low-power computation
+
** High-performance custom-computing processors/systems
−
- Reconfigurable/configurable hardware and systems including
+
** Novel architectures and device technologies that can be applied to efficient acceleration, including many-core architectures, NoC architectures, 3D-stacking technologies and optical devices
−
IP-cores, embedded systems, SoCs and cluster/grid/cloud computing
 
−
systems for scalable, high-performance and/or low-power processing
 
−
- High-performance custom-computing processors/systems
 
−
- Novel architectures and device technologies that can be applied to
 
−
efficient acceleration, including many-core architectures, NoC
 
−
architectures, 3D-stacking technologies and optical devices
 
  
 
* Software and applications:
 
* Software and applications:
−
- Novel applications for efficient acceleration systems/platforms,
+
** Novel applications for efficient acceleration systems/platforms, and custom computing
−
and custom computing
+
** Compiler techniques and programming languages for efficient acceleration systems/platforms, including many-core processors, GPUs, FPGAs and other reconfigurable/custom processors
−
- Compiler techniques and programming languages for efficient
+
** Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
−
acceleration systems/platforms, including many-core processors,
+
** Performance evaluation and analysis for efficient acceleration
−
GPUs, FPGAs and other reconfigurable/custom processors
+
** High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems.
−
- Run-time techniques for acceleration, including Just-in-Time
 
−
compilation and dynamic partial-reconfiguration
 
−
- Performance evaluation and analysis for efficient acceleration
 
−
- High-level synthesis and design methodologies for heterogeneous,
 
−
reconfigurable and/or custom processors/systems.
 
  
 
==Submissions==
 
==Submissions==
Line 87: Line 76:
 
==Committees==
 
==Committees==
 
*Workshop Co-chairs:
 
*Workshop Co-chairs:
−
- Hideharu Amano, Keio University, JP
+
** Hideharu Amano, Keio University, JP
−
- Wayne Luk, Imperial College London, UK
+
** Wayne Luk, Imperial College London, UK
  
 
*Program Co-chairs:
 
*Program Co-chairs:
−
- Walid Najjar, University of California Riverside, US
+
** Walid Najjar, University of California Riverside, US
−
- Yukinori Sato, JAIST, JP
+
** Yukinori Sato, JAIST, JP
−
- David Thomas, Imperial College London, UK
+
** David Thomas, Imperial College London, UK
  
 
*Publication Co-chairs:
 
*Publication Co-chairs:
−
- Yuichiro Shibata, Nagasaki University, JP
+
** Yuichiro Shibata, Nagasaki University, JP
−
- Hironori Nakajo, Tokyo University of Agriculture and Technology, JP
+
** Hironori Nakajo, Tokyo University of Agriculture and Technology, JP
  
 
*Publicity Co-chairs:
 
*Publicity Co-chairs:
−
- Yoshiki Yamaguchi, University of Tsukuba, JP
+
** Yoshiki Yamaguchi, University of Tsukuba, JP
−
- Khaled Benkrid, the University of Edinburgh, UK
+
** Khaled Benkrid, the University of Edinburgh, UK
−
- Qiang Liu, Tianjin University, CN
+
** Qiang Liu, Tianjin University, CN
  
 
*Finance Chair:
 
*Finance Chair:
−
- Kentaro Sano, Tohoku University, JP
+
** Kentaro Sano, Tohoku University, JP
  
 
*Local Arrangement Chair:
 
*Local Arrangement Chair:
−
- Yasunori Osana, University of Ryukyu, JP
+
** Yasunori Osana, University of Ryukyu, JP
  
 
*Design Contest Co-chairs:
 
*Design Contest Co-chairs:
−
- Tomonori Izumi, Ritsumeikan University, JP
+
** Tomonori Izumi, Ritsumeikan University, JP
−
- Minoru Watanabe, Shizuoka University, JP
+
** Minoru Watanabe, Shizuoka University, JP
  
 
*Program Committee:
 
*Program Committee:
−
- Ali Akoglu, University of Arizona, USA
+
** Ali Akoglu, University of Arizona, USA
−
- Philip Brisk, University of California, Riverside, USA
+
** Philip Brisk, University of California, Riverside, USA
−
- Florent de Dinechin, Ecole Normale Supérieure de Lyon, FR
+
** Florent de Dinechin, Ecole Normale Supérieure de Lyon, FR
−
- Yajun Ha, National University of Singapore, SG
+
** Yajun Ha, National University of Singapore, SG
−
- Martin Herbordt, Boston University, USA
+
** Martin Herbordt, Boston University, USA
−
- Yohei Hori, National Institute of Advanced Industrial Science and Technology, JP
+
** Yohei Hori, National Institute of Advanced Industrial Science and Technology, JP
−
- Paolo Ienne, EPFL, CH
+
** Paolo Ienne, EPFL, CH
−
- Tomonori Izumi, Ritsumeikan University, JP
+
** Tomonori Izumi, Ritsumeikan University, JP
−
- Nachiket Kapre, Imperial College London, UK
+
** Nachiket Kapre, Imperial College London, UK
−
- Dirk Koch, University of Oslo, NO
+
** Dirk Koch, University of Oslo, NO
−
- Herman Lam, University of Florida, USA
+
** Herman Lam, University of Florida, USA
−
- Philip Leong, University of Sydney, AU
+
** Philip Leong, University of Sydney, AU
−
- Tsutomu Maruyama, University of Tsukuba, JP
+
** Tsutomu Maruyama, University of Tsukuba, JP
−
- Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR
+
** Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR
−
- Miquel Pericás, Tokyo Institute of Technology, JP
+
** Miquel Pericás, Tokyo Institute of Technology, JP
−
- Gregory Peterson, University of Tenessee, USA
+
** Gregory Peterson, University of Tenessee, USA
−
- Hayden Kwok-Hay So, University of Hong Kong, HK
+
** Hayden Kwok-Hay So, University of Hong Kong, HK
−
- Yiannis Sourdis, Chalmers University of Technology, SE
+
** Yiannis Sourdis, Chalmers University of Technology, SE
−
- Henry Styles, Xilinx, USA
+
** Henry Styles, Xilinx, USA
−
- Bharat Sukhwani, IBM T. J. Watson Research Center, USA
+
** Bharat Sukhwani, IBM T. J. Watson Research Center, USA
−
- Thomas D. VanCourt, Akamai Technologies, USA
+
** Thomas D. VanCourt, Akamai Technologies, USA
−
- Wim Vanderbauwhede, Glasgow University, UK
+
** Wim Vanderbauwhede, Glasgow University, UK
−
- Minoru Watanabe, Shizuoka University, JP
+
** Minoru Watanabe, Shizuoka University, JP
−
- Stephan Wong, Delft University of Technology, NL
+
** Stephan Wong, Delft University of Technology, NL
−
- Masato Yoshimi, Doshisha University, JP
+
** Masato Yoshimi, Doshisha University, JP
−
- Chiwai Yu, City University of Hong Kong, Hong Kong, HK
+
** Chiwai Yu, City University of Hong Kong, Hong Kong, HK

Latest revision as of 12:22, 29 January 2012

HEART 2012
Highly Efficient Accelerators and Reconfigurable Technologies
Dates 2012/05/31 (iCal) - 2012/06/01
Homepage: www.isheart.org/HEART2012
Location
Location: Naha, Okinawa, Japan
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Important dates
Submissions: 2012/02/21
Table of Contents


Call for Papers

The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies -- HEART2012 -- Okinawa, Japan May 30 - June 1, 2012 (http://www.isheart.org)

Important Dates

  • Paper submission: February 21, 2012
  • Author notification: March 26, 2012
  • Design contest entry: March 26, 2012
  • Camera-ready due: April 12, 2012
  • Design contest: May 30, 2012
  • Workshop date: May 31 - June 1, 2012

Topics

The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART) is a forum to present and discuss new research on accelerators and the use of reconfigurable technologies for high-performance and/or power-efficient computation. Submissions are solicited on a wide variety of topics related to the acceleration for high-performance computation, including but not limited to:

  • Architectures and systems:
    • Novel systems/platforms for efficient acceleration based on FPGA, GPU, CELL/B.E and other devices
    • Heterogeneous processors/systems for scalable, high-performance, high-reliability and/or low-power computation
    • Reconfigurable/configurable hardware and systems including IP-cores, embedded systems, SoCs and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
    • High-performance custom-computing processors/systems
    • Novel architectures and device technologies that can be applied to efficient acceleration, including many-core architectures, NoC architectures, 3D-stacking technologies and optical devices
  • Software and applications:
    • Novel applications for efficient acceleration systems/platforms, and custom computing
    • Compiler techniques and programming languages for efficient acceleration systems/platforms, including many-core processors, GPUs, FPGAs and other reconfigurable/custom processors
    • Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
    • Performance evaluation and analysis for efficient acceleration
    • High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems.

Submissions

We will accept regular and short papers for oral and poster presentation, respectively. All the accepted regular papers will be published in the post-proceedings that will be published as a special issue of ACM SIGARCH Computer Architecture News (CAN) and will also be available in ACM Digital Library. By submitting your work to the HEART2012 workshop, you grant permission for ACM to publish the material in print and digital formats in ACM's Computer Architecture News and the ACM archive. The short papers will be included in the workshop handout distributed at the workshop. One of the authors must attend the workshop and present their work as a condition of publication.

All papers must be no more than 6 pages (two columns, US letter size, 10 points for main body text) in length and prepared in PDF format. For double-blind review, manuscripts must NOT identify authors; names of authors, affiliations, e-mail addresses and self-references should be blanked out. Papers that identify authors may be rejected without review. Full formatting and submission instructions are available at the HEART2012 web-site.

For more information, please visit (http://www.isheart.org/).

Committees

  • Workshop Co-chairs:
    • Hideharu Amano, Keio University, JP
    • Wayne Luk, Imperial College London, UK
  • Program Co-chairs:
    • Walid Najjar, University of California Riverside, US
    • Yukinori Sato, JAIST, JP
    • David Thomas, Imperial College London, UK
  • Publication Co-chairs:
    • Yuichiro Shibata, Nagasaki University, JP
    • Hironori Nakajo, Tokyo University of Agriculture and Technology, JP
  • Publicity Co-chairs:
    • Yoshiki Yamaguchi, University of Tsukuba, JP
    • Khaled Benkrid, the University of Edinburgh, UK
    • Qiang Liu, Tianjin University, CN
  • Finance Chair:
    • Kentaro Sano, Tohoku University, JP
  • Local Arrangement Chair:
    • Yasunori Osana, University of Ryukyu, JP
  • Design Contest Co-chairs:
    • Tomonori Izumi, Ritsumeikan University, JP
    • Minoru Watanabe, Shizuoka University, JP
  • Program Committee:
    • Ali Akoglu, University of Arizona, USA
    • Philip Brisk, University of California, Riverside, USA
    • Florent de Dinechin, Ecole Normale Supérieure de Lyon, FR
    • Yajun Ha, National University of Singapore, SG
    • Martin Herbordt, Boston University, USA
    • Yohei Hori, National Institute of Advanced Industrial Science and Technology, JP
    • Paolo Ienne, EPFL, CH
    • Tomonori Izumi, Ritsumeikan University, JP
    • Nachiket Kapre, Imperial College London, UK
    • Dirk Koch, University of Oslo, NO
    • Herman Lam, University of Florida, USA
    • Philip Leong, University of Sydney, AU
    • Tsutomu Maruyama, University of Tsukuba, JP
    • Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR
    • Miquel Pericás, Tokyo Institute of Technology, JP
    • Gregory Peterson, University of Tenessee, USA
    • Hayden Kwok-Hay So, University of Hong Kong, HK
    • Yiannis Sourdis, Chalmers University of Technology, SE
    • Henry Styles, Xilinx, USA
    • Bharat Sukhwani, IBM T. J. Watson Research Center, USA
    • Thomas D. VanCourt, Akamai Technologies, USA
    • Wim Vanderbauwhede, Glasgow University, UK
    • Minoru Watanabe, Shizuoka University, JP
    • Stephan Wong, Delft University of Technology, NL
    • Masato Yoshimi, Doshisha University, JP
    • Chiwai Yu, City University of Hong Kong, Hong Kong, HK
Retrieved from "https://www.openresearch.org/mediawiki/index.php?title=HEART_2012&oldid=23288"
Facts about "HEART 2012"
RDF feed
AcronymHEART 2012 +
End dateJune 1, 2012 +
Event typeWorkshop +
Has coordinates26° 12' 44", 127° 40' 45"Latitude: 26.212233333333
Longitude: 127.67914444444 +
Has location cityNaha +
Has location countryCategory:Japan +
Has location stateOkinawa +
Homepagehttp://www.isheart.org/HEART2012 +
IsAEvent +
Start dateMay 31, 2012 +
Submission deadlineFebruary 21, 2012 +
TitleHighly Efficient Accelerators and Reconfigurable Technologies +