Difference between revisions of "ASP-DAC 2020"

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<!-- PLEASE ADAPT OR DELETE THIS PART COMPLETELY - You can just paste in the call for papers and remove this and the last line
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==Call for Papers ASP-DAC 2020==
  
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==Topics==
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Areas of Interest:
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==Submissions==
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Original papers in, but not limited to, the following areas are invited.
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==Important Dates==
 
  
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==Committees==
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1. System-Level Modeling and Design Methodology:
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* Co-Organizers
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1.1. HW/SW co-design, co-simulation and co-verification
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* General Co-Chairs
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1.2. System-level design exploration, synthesis and optimization
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** [[has general chair::some person]], some affiliation, country
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1.3. System-level formal verification
 +
1.4. System-level modeling, simulation and validation tools/methodology
  
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* PC Co-Chairs
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2. Embedded Systems and Cyberphysical Systems:
−
** [[has program chair::some person]], some affiliation, country
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2.1. Many- and multi-core SoC architecture
 +
2.2. IP/platform-based SoC design
 +
2.3. Domain-specific architecture
 +
2.4. Dependable architecture
 +
2.5. Cyber physical system
 +
2.6. Internet of things
  
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* Workshop Chair
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3. Embedded Systems Software:
−
** [[has workshop chair::some person]], some affiliation, country
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3.1. Kernel, middleware and virtual machine
 +
3.2. Compiler and toolchain
 +
3.3. Real-time system
 +
3.4. Resource allocation for heterogeneous computing platform
 +
3.5. Storage software and application
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3.6. Human-computer interface
  
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* Panel Chair
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4. Memory Architecture and Near/In Memory Computing:
−
** [[has OC member::some person]], some affiliation, country
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4.1. Storage system and memory architecture
 +
4.2. On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc.
 +
4.3. Memory and storage hierarchies with emerging memory technologies
 +
4.4. Near-memory and in-memory computing
 +
4.5. Memory architecture and management for emerging memory technologies
  
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* Seminars Chair
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5. Neural Network and Neuromorphic Computing:
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** [[has tutorial chair::some person]], some affiliation, country
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5.1. Hardware and devices for neuromorphic and neural network computing
 +
5.2. Design method for learning on a chip
 +
5.3. Systems for neural computing (including deep neural networks)
 +
5.4. Neural network acceleration techniques including GPGPU, FPGA and dedicated ASICs
 +
5.5. CAD for bio-inspired and neuromorphic systems
  
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* Demonstration Co-Chairs
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6. Analog, RF, Mixed Signal, and Photonics:
−
** [[has demo chair::some person]], some affiliation, country
+
6.1. Analog/mixed-signal/RF synthesis
−
** [[has demo chair::some person]], some affiliation, country
+
6.2. Analog layout, verification, and simulation techniques
 +
6.3. High-frequency electromagnetic simulation of circuit
 +
6.4. Mixed-signal design consideration
 +
6.5. Communication architectures using nanophotonics, RF, 3D, etc.
 +
6.6. Networks-on-chip and NoC-based system design
  
−
* Local Organizing Co-Chairs
+
7. Lower Power Design and Approximate Computing:
−
** [[has local chair::some person]], some affiliation, country
+
7.1. Power modeling, analysis and simulation
 +
7.2. Low-power design and methodology
 +
7.3. Thermal aware design
 +
7.4. Energy harvesting and battery management
 +
7.5. Hardware techniques for approximate/stochastic computing
  
−
* Program Committee Members
+
8. Logic/High-Level Synthesis and Optimization:
−
** [[has PC member::some person]], some affiliation, country
+
8.1. High-level synthesis tool and methodology
−
-->
+
8.2. Combinational, sequential and asynchronous logic synthesis
 +
8.3. Logic synthesis and physical design technique for FPGA
 +
8.4. Technology mapping
 +
 
 +
9. Physical Design:
 +
9.1. Floorplanning, partitioning and placement
 +
9.2. Interconnect planning and synthesis
 +
9.3. Placement and routing optimization
 +
9.4. Clock network synthesis
 +
9.5. Post layout and post-silicon optimization
 +
9.6. Package/PCB/3D-IC routing
 +
 
 +
10. Design for Manufacturability and Reliability:
 +
10.1. Reticle enhancement, lithography-related design and optimization
 +
10.2. Resilience under manufacturing variation
 +
10.3. Design for manufacturability, yield, and defect tolerance
 +
10.4. Reliability, aging and soft error analysis
 +
10.5. Design for reliability, aging, and robustness
 +
10.6. Machine learning for smart manufacturing and process control
 +
 
 +
11. Timing and Signal/Power Integrity:
 +
11.1. Deterministic/statistical timing and performance analysis and optimization
 +
11.2. Power/ground and package modeling, analysis and optimization
 +
11.3. Signal/power integrity, EM modeling and analysis
 +
11.4. Extraction, TSV and package modeling
 +
11.5. 2D/3D on-chip power delivery network analysis and optimization
 +
 
 +
12. Testing, Validation, Simulation, and Verification:
 +
12.1. ATPG, BIST and DFT
 +
12.2. System test and 3D IC test
 +
12.3. Online test and fault tolerance
 +
12.4. Memory test and repair
 +
12.5. RTL and gate-leveling modeling, simulation, and verification
 +
12.6. Circuit-level formal verification
 +
12.7. Device/circuit-level simulation tool and methodology
 +
 
 +
13. Hardware and Embedded Security:
 +
13.1. Hardware-based security
 +
13.2. Detection and prevention of hardware Trojans
 +
13.3. Side-channel attacks, fault attacks and countermeasures
 +
13.4. Design and CAD for security
 +
13.5. Cyberphysical system security
 +
13.6. Nanoelectronic security
 +
13.7. Supply chain security and anti-counterfeiting
 +
 
 +
14. Emerging Technologies and Applications:
 +
14.1. Biomedical, biochip, and biodata processing
 +
14.2. Big/thick data, datacenter
 +
14.3. Advanced multimedia application
 +
14.4. Energy-storage/smart-grid/smart-building design and optimization
 +
14.5. Automotive system design and optimization
 +
14.6. New transistor/device and process technology: spintronic, phase-change, single-electron etc.
 +
14.7. Nanotechnology, MEMS, quantum computing etc.
 +
 
 +
Please note that each paper shall be accompanied by at least one different conference registration at the speaker’s registration rate (e.g., two speaker registrations are needed for presenting two accepted papers). But any registered co-author can present the work at the conference. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by the author of the paper. ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, and journals.
 +
 
 +
Submission of Papers:
 +
 
 +
Deadline for abstract: 5 PM AOE (Anywhere on earth) July 5 (Fri), 2019
 +
 
 +
Deadline for full paper: 5 PM AOE (Anywhere on earth) July 5 (Fri), 2019 July 12 (Fri), 2019 (extended)
 +
 
 +
Notification of acceptance: Sep. 9 (Mon), 2019
 +
 
 +
Deadline for final version: 5 PM AOE (Anywhere on earth) Nov. 4 (Mon), 2019
 +
 
 +
For detailed instructions for submission and specification of the paper format, please refer to Author's Guide.

Revision as of 13:26, 13 May 2020

ASP-DAC 2020
25th Asia and South Pacific Design Automation Conference
Event in series ASP-DAC
Dates 2020/01/13 (iCal) - 2020/01/16
Homepage: https://aspdac2020.github.io/aspdac20/
Location
Location: Beijing, China
Loading map...

Important dates
Submissions: 2019/07/12
Committees
General chairs: K.-T. Tim Cheng, Huazhong Yang
PC chairs: Tsung-Yi Ho
Table of Contents


Call for Papers ASP-DAC 2020

Areas of Interest: Original papers in, but not limited to, the following areas are invited.

1. System-Level Modeling and Design Methodology: 1.1. HW/SW co-design, co-simulation and co-verification 1.2. System-level design exploration, synthesis and optimization 1.3. System-level formal verification 1.4. System-level modeling, simulation and validation tools/methodology

2. Embedded Systems and Cyberphysical Systems: 2.1. Many- and multi-core SoC architecture 2.2. IP/platform-based SoC design 2.3. Domain-specific architecture 2.4. Dependable architecture 2.5. Cyber physical system 2.6. Internet of things

3. Embedded Systems Software: 3.1. Kernel, middleware and virtual machine 3.2. Compiler and toolchain 3.3. Real-time system 3.4. Resource allocation for heterogeneous computing platform 3.5. Storage software and application 3.6. Human-computer interface

4. Memory Architecture and Near/In Memory Computing: 4.1. Storage system and memory architecture 4.2. On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc. 4.3. Memory and storage hierarchies with emerging memory technologies 4.4. Near-memory and in-memory computing 4.5. Memory architecture and management for emerging memory technologies

5. Neural Network and Neuromorphic Computing: 5.1. Hardware and devices for neuromorphic and neural network computing 5.2. Design method for learning on a chip 5.3. Systems for neural computing (including deep neural networks) 5.4. Neural network acceleration techniques including GPGPU, FPGA and dedicated ASICs 5.5. CAD for bio-inspired and neuromorphic systems

6. Analog, RF, Mixed Signal, and Photonics: 6.1. Analog/mixed-signal/RF synthesis 6.2. Analog layout, verification, and simulation techniques 6.3. High-frequency electromagnetic simulation of circuit 6.4. Mixed-signal design consideration 6.5. Communication architectures using nanophotonics, RF, 3D, etc. 6.6. Networks-on-chip and NoC-based system design

7. Lower Power Design and Approximate Computing: 7.1. Power modeling, analysis and simulation 7.2. Low-power design and methodology 7.3. Thermal aware design 7.4. Energy harvesting and battery management 7.5. Hardware techniques for approximate/stochastic computing

8. Logic/High-Level Synthesis and Optimization: 8.1. High-level synthesis tool and methodology 8.2. Combinational, sequential and asynchronous logic synthesis 8.3. Logic synthesis and physical design technique for FPGA 8.4. Technology mapping

9. Physical Design: 9.1. Floorplanning, partitioning and placement 9.2. Interconnect planning and synthesis 9.3. Placement and routing optimization 9.4. Clock network synthesis 9.5. Post layout and post-silicon optimization 9.6. Package/PCB/3D-IC routing

10. Design for Manufacturability and Reliability: 10.1. Reticle enhancement, lithography-related design and optimization 10.2. Resilience under manufacturing variation 10.3. Design for manufacturability, yield, and defect tolerance 10.4. Reliability, aging and soft error analysis 10.5. Design for reliability, aging, and robustness 10.6. Machine learning for smart manufacturing and process control

11. Timing and Signal/Power Integrity: 11.1. Deterministic/statistical timing and performance analysis and optimization 11.2. Power/ground and package modeling, analysis and optimization 11.3. Signal/power integrity, EM modeling and analysis 11.4. Extraction, TSV and package modeling 11.5. 2D/3D on-chip power delivery network analysis and optimization

12. Testing, Validation, Simulation, and Verification: 12.1. ATPG, BIST and DFT 12.2. System test and 3D IC test 12.3. Online test and fault tolerance 12.4. Memory test and repair 12.5. RTL and gate-leveling modeling, simulation, and verification 12.6. Circuit-level formal verification 12.7. Device/circuit-level simulation tool and methodology

13. Hardware and Embedded Security: 13.1. Hardware-based security 13.2. Detection and prevention of hardware Trojans 13.3. Side-channel attacks, fault attacks and countermeasures 13.4. Design and CAD for security 13.5. Cyberphysical system security 13.6. Nanoelectronic security 13.7. Supply chain security and anti-counterfeiting

14. Emerging Technologies and Applications: 14.1. Biomedical, biochip, and biodata processing 14.2. Big/thick data, datacenter 14.3. Advanced multimedia application 14.4. Energy-storage/smart-grid/smart-building design and optimization 14.5. Automotive system design and optimization 14.6. New transistor/device and process technology: spintronic, phase-change, single-electron etc. 14.7. Nanotechnology, MEMS, quantum computing etc.

Please note that each paper shall be accompanied by at least one different conference registration at the speaker’s registration rate (e.g., two speaker registrations are needed for presenting two accepted papers). But any registered co-author can present the work at the conference. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by the author of the paper. ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, and journals.

Submission of Papers:

Deadline for abstract: 5 PM AOE (Anywhere on earth) July 5 (Fri), 2019

Deadline for full paper: 5 PM AOE (Anywhere on earth) July 5 (Fri), 2019 July 12 (Fri), 2019 (extended)

Notification of acceptance: Sep. 9 (Mon), 2019

Deadline for final version: 5 PM AOE (Anywhere on earth) Nov. 4 (Mon), 2019

For detailed instructions for submission and specification of the paper format, please refer to Author's Guide.

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Facts about "ASP-DAC 2020"
RDF feed
AcronymASP-DAC 2020 +
End dateJanuary 16, 2020 +
Event in seriesASP-DAC +
Event typeConference +
Has coordinates40° 11' 26", 116° 24' 44"Latitude: 40.190633333333
Longitude: 116.41214444444 +
Has general chairK.-T. Tim Cheng + and Huazhong Yang +
Has location cityBeijing +
Has location countryCategory:China +
Has program chairTsung-Yi Ho +
Homepagehttps://aspdac2020.github.io/aspdac20/ +
IsAEvent +
Start dateJanuary 13, 2020 +
Submission deadlineJuly 12, 2019 +
Title25th Asia and South Pacific Design Automation Conference +